The Local Oxidation Of Silicon (LOCOS) process using a nitride layer has been used as an isolation technology for manufacturing semiconductor devices. However, the LOCOS process has a drawback in that it causes a phenomenon wherein a silicon oxide layer in the general shape of a bird's beak makes inroads into an active region. In order to complete the LOCOS process, new isolation technologies have been developed. Among these new technologies, a Poly Buffer LOCOS (PBL), a Recessed LOCOS (R-LOCOS) and other processes have been widely used. However, these technologies also have drawbacks in that these processes are complicated and they do not prevent the bird's beak phenomenon. Thus, the bird's beak phenomenon limits high-integration of semiconductor devices. Furthermore, since a considerable step between the surfaces of the oxide layer on the active region and a field region of the silicon substrate is generated, a planarizing process should be successively performed to reduce the step between the surfaces of the regions.
Recently, an improved Shallow Trench Isolation (STI) process has been introduced. The STI process has advantages in that it achieves an excellent isolation property and a small occupying area so that, when compared with conventional isolation technology, using the STI process is very advantageous in promoting high-integration of semiconductor devices.
The STI process is performed by forming a trench on a field region of a semiconductor substrate, filling the trench with a gap-filling oxide layer, and performing a Chemical Mechanical Polishing (CMP) of the oxide layer so as to planarize the oxide layer. Accordingly, a field oxide layer is formed in the trench of the field region of the semiconductor substrate.
The oxide layer that fills the trench generally includes an O3-Tetra-Ethyl-Ortho—Silicate (TEOS) Atmospheric Pressure Chemical Vapor Deposition (APCVD) oxide layer and a High Density Plasma Chemical Vapor Deposition (HDP CVD) oxide layer, which have excellent filling and planarizing properties.
However, when the prior art STI process has been completed, divots have frequently been generated in the oxide layer near an upper corner portion of the trench. Furthermore, since the upper corner portion generally has an angular shape, a gate oxide layer is grown thinner on an edge portion of the active region adjacent to the upper corner portion than on the other portions of the active region. Thus, an electric field is concentrated at the edge portion of the active region, so that degradation of an electrical characteristic and increased leakage current is caused.
Recently, in consideration of this problem, a method of preventing the concentration of the electric field at the edge portion of the active region has been proposed. This proposed method seeks to prevent the noted electric field concentration by making the upper edge portion of the trench round. To this end, a pull back process is employed to wet-etch a nitride layer, (an intermediate layer of an etching mask for forming the trench), transversely.
The conventional STI process using this pull back process is conducted as shown in FIG. 1. First, an oxide layer 11, a nitride layer 13 and an oxide layer 15 are successively deposited on a semiconductor substrate 10 such as a single crystal silicon substrate. Then, using photolithography, an opening 16 is formed in the oxide layer 11, the nitride layer 13 and the oxide layer 15 above the field region of the semiconductor substrate 10. Then, using the oxide layer 15 as an etching mask, the field region of the semiconductor substrate 10 is etched to a depth of 3000 to 4000 Å, so that a trench 17 is formed in the field region of the semiconductor substrate 10.
As shown in FIG. 2, using the pull back process, the nitride layer 13 is etched a distance D of 200 to 300 Å from the opening 16 by a phosphate solution, so that a groove 18 is formed on the edge portion of the nitride layer 13 between the two oxide layers 11 and 15. By filling the groove 18 with an oxide layer 19, it is possible to prevent generation of divots in the oxide layer 19 during a subsequent procedure of wet-etching the oxide layer.
As shown in FIG. 3, using a conventional low pressure CVD process, O3-TEOS CVD process, or HDP CVD process, the oxide layer 19 is deposited on the surfaces of the insulating layer 15, the trench 17 and the groove 18 in a thickness required for gap-filling the trench 17, (for example, 5000 to 6000 Å).
Although not shown in the drawings, using a conventional CMP process, the oxide layer 19 is planarized and the oxide layer 15, the nitride layer 13 and the oxide layer 11 are etched to expose the surface of the active region of the semiconductor substrate 10, thus, completing the STI process.
However, in the prior art method, when the trench 17 is filled with the oxide layer 19, the oxide layer 19 is likely to not completely fill the groove 18 due to the aspect ratio of the groove. As a result, voids may possibly be generated in the oxide layer 19 in the groove 18. As a result, divots may be generated in the oxide layer 19 in the trench 17, thereby increasing the leakage current of the semiconductor device and deteriorating an electric characteristic thereof.
In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description of the same or similar components will be omitted.